Custom memory component trouble in SOPC builder

I just switched to Quartus 7.2 and have a trouble with custom external memory component creation.

First, I started the new component editor and created the Avalon tristate slave and then created a few signals for custom component:

address [10] (input)

data [8] (bidir)

cs_n

oe_n

wr_n

The avalon MM tristate bridge was instantiated and connected to NIOS II cpu with internal RAM memory

The custom memory component was connected to 'master' side of that bridge.

No warning were issued and system was generaed OK.

But only data port appeared in top level design !!!

The same works OK in Q 6.1.

Did anybody met this problem?

Regards,

andrew