Forum Discussion
AndrewH
New Contributor
New ContributorCurious optimization of a reset circuit
I have seen a number of posts about creating a suitable reset.
The attached notes shows one successful attempt (testcase-2).
However, I am at a loss as to why testcase-3 fails.
I thought I woul...
RichardT_altera
Super Contributor
Super ContributorI will need to discuss with the internal team related to the power-on-reset. Please allow me some time to work on it.
- RichardT_altera
After discussion, we don't usually create POR as it is a part of the FPGA.
I think the user guide below may help to explain how the power-on reset circuitry works in MAX10 fpga.
Or you are asking about Asynchronous & Synchronous Reset design? Perhaps this paper may help to explain.
http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
