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any z(-1) block is one register delay stage.
you will need four pipes:
Re * coffRe
Re * coeffim
im *coeffRe
im * coeffIm
The final Re and Im outputs are as explained in my first post.
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hey as my guide suggested i should focus on implementing a multiplierless correlator for that i designed it in matlab so that i know if i give two inputs what output a correlator gives so for example i gave 29 and 8 the answer was 232 so in order to design it in vlsi i have to do this multiplication via shift and add and for that i have been studying techniques and there is always an error somewhere a carry lefts off and in some cases answer not correct..suggest me some techniques if you will. as now i am focusing on creating multiplierless correlator without multiplication and then do performance analysis of those techniques
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