Honored ContributorHi,
I'm working on a design converting from Xilinx to Altera. The following constrain is being used in the Xilinx UCF file. NET "clk_250_n_bufg" TNM_NET = "clk_250_n" ; TIMESPEC "TS_clk_250_n" = PERIOD "clk_250_n" TS_clk_125 / 2 PHASE - 2 ns HIGH 50 %; Can you use a negative rising and falling waveform edge, when creating a clock in TimeQuest? Thanks!
Honored ContributorCan you elaborate what you're trying to do? Naturally, a clock won't just shift -2ns. If it's a PLL doing it, then derive_pll_clocks should do it, or you can do your own generated clock. If it's another clock coming into the FPGA at a top-level port, then generally a create_clock will do it(although a generated clock can be used). Note that TimeQuest does not have negative edges, so I can explain this one in more detail if it's what you're trying to do.
As for the comment about rising/falling edges, TQ is fully aware of this and a clock constraint automatically creates rising and falling edges, and setup/hold relationships between all combinations.
