Forum Discussion

07dshaffer's avatar
07dshaffer
Icon for New Contributor rankNew Contributor
5 years ago

Creating BSF strips parentheses from output signal size

When I attempt to generate a BSF using the following system verilog code, Quartus 20.1 Prime Lite is stripping the parentheses from the calculation of the output signal size. This results in an incor...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Engineering has made preliminary plan to fix this issue in Quartus Standard version 21.1 which will be released around September. Until then you will have to use the workaround of editing the symbol after regenerating it.

With that being said, I will put this case to a close pending. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,

Nurina