Forum Discussion

New Contributor

5 years ago

Creating BSF strips parentheses from output signal size

When I attempt to generate a BSF using the following system verilog code, Quartus 20.1 Prime Lite is stripping the parentheses from the calculation of the output signal size. This results in an incor...

Nurina

Regular Contributor

5 years ago

Hi,

Engineering has investigated root cause. However, they are now focusing feature enhancement/bug fixing on Pro edition. For standard, they will put it as lower priority. This fix will take some time . We are sorry to inform this.

With that, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,

Nurina

Forum Discussion

Creating BSF strips parentheses from output signal size

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