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07dshaffer's avatar
07dshaffer
Icon for New Contributor rankNew Contributor
5 years ago

Creating BSF strips parentheses from output signal size

When I attempt to generate a BSF using the following system verilog code, Quartus 20.1 Prime Lite is stripping the parentheses from the calculation of the output signal size. This results in an incor...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Sometimes there are problems with generating block symbols from HDL and vice versa. I've reproduced your error and am reporting this issue to engineering.


Regards,

Nurina