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Altera_Forum
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16 years ago

Creating a time delay in Quartus

Hi everyone, I currently have an fpga design for a nios 2 cyclone 1. I have a signal which comes from a different board and has a frequency of 12.5kHz. I need to create another signal which is ...
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Altera_Forum
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16 years ago

The usual way is to delay both signal edges by a defined number of system clock cycles, requires a counter an a state machine. Because the delayed signal transitions are at discrete times, you create a delay jitter of +/- 0.5 system clock cycles.