Creating a new IP component with VHDL design using a customized library

I have added all the files if the library "Lib" but I have the same error message. I think that the tool doesn't like user libraries. With Quartus I was able to add all the design files (in VHDL) of "Lib" and to define them as a library then the compilation of the top level design in VHDL was successful. So what I am looking for is how to do the same with QSYS because I can add the files but I don't know how to declare them as library "Lib".