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Altera_Forum
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8 years ago

Creating a new IP component with VHDL design using a customized library

Hello, I am trying to create a new component using Component Editor of Qsys. Actually, the top level design of the new component calls a library "Lib" that I have created and uses a pckage defi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Yes, just like if you were to synthesize this in Quartus, you have to add all of your files to the Files tab of the Component Editor.