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In Vhdl there are not these problems....you can try to create a project_top.vhdl in which you istanziate other sub-modules....mux,decoder,registers...for your custom design....every module can be istanziated many times...even if it has the same name declared in its sub_module.vhdl file
For example...
Project-top.vhdl
Reg.vhdl
Dec.vhdl
Mux.vhdl
In Project-top.vhdl you can istanziate Reg.vhdl, for example, there Times
Component Reg
Port();
End component;
Component Dec
Port();
End component;
Component Mux
Port();
End component;
Inst1: Reg
Port map();
Inst2: Reg
Port map();
Inst3: Reg
Port map();
Inst4: Dec
Port map();
Inst5: Mux
Port map();
So...their names Are not important to define...you can use every module you design..eveywhere...
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Thank you for your reply. I believe I understand what you're saying and I think you can do this with the schematic editor as well.
But lets say I've already started a project and I'm working on a sub module deep within a few layers of hierarchy down. When I'm done making edits, I'd like to take that module from within the design and pass it off to someone else. I want to make sure I grab only the files associated with that one module.
Or even the case where I start a module in a brand new project and want to integrate it into an existing project. I need to make sure that the module I'm importing has all unique names. Otherwise my "Reg.vhd" from the module I'm importing will overwrite my "Reg.vhd" I already have defined in the project (Which can have a different meaning/number of bits lets say)
Honored Contributor
