Creating A Modular Design

In Vhdl there are not these problems....you can try to create a project_top.vhdl in which you istanziate other sub-modules....mux,decoder,registers...for your custom design....every module can be istanziated many times...even if it has the same name declared in its sub_module.vhdl file

For example...

Project-top.vhdl

Reg.vhdl

Dec.vhdl

Mux.vhdl

In Project-top.vhdl you can istanziate Reg.vhdl, for example, there Times

Component Reg

Port();

End component;

Component Dec

Port();

End component;

Component Mux

Port();

End component;

Inst1: Reg

Port map();

Inst2: Reg

Port map();

Inst3: Reg

Port map();

Inst4: Dec

Port map();

Inst5: Mux

Port map();

So...their names Are not important to define...you can use every module you design..eveywhere...