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I gave the timing parameters as TSU 3.33 ns and TCO 3.33ns and Max frequency 300Mhz.
After implementation, results shows TCO is 5.071ns (191Mhz).
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I think you have a misunderstanding of how Tco is computed and what it represents with respect to overall system timing.
* Tco is the amount of time between a clock signal's arrival at the FPGA and the corresponding transition of an output pin that is driven (directly or indirectly) by a signal clocked by the aforementioned clock signal.
* Fmax is the maximum clock frequency that you can apply without violating the setup requirements of any register in the design.
A 300 MHz Fmax constraint does not imply a 3.33ns Tco constraint, nor does a 3.33ns Tco constraint imply a 300 MHz Fmax constraint. When the tool reports that your design has a Tco of 5.071ns, that doesn't imply Fmax is limited to 191MHz (1/5.071ns). Actually, it doesn't imply anything about Fmax.
As another poster mentioned, Tco timing is (typically) only important when your system is trying to latch the output signal's data to another register sourced by the same clock. Based on your problem specifications, I don't believe you need to specify a Tco constraint (nor a Tsu constraint) in order to satisfy your design requirements.
- Mark
Honored Contributor
