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Altera_Forum's avatar
Altera_Forum
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17 years ago

counter clock latency

I am new to QuartusII tool. My requirement is to design 16 bit up counter and implement STARTIX II device with 1 clock cycle latency at 300Mhz with Quartus II tool. I written simple code...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I doubt, if the design can work as intended. You can't count on a static input signal 

if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then

If you performed timing analysis on this design, it won't give any meaningful results.

An operational counter is like this: 

if clear = '1' then
Pre_Q <= (others => '0');
elsif (clock='1' and clock'event) then