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It will be neither. It will problems with the design and your coding. The way you say latch - is it really a latch (like a transparent latch) or are they registers.
If you could post the code, we could help much more. The code doesnt look like its anything special really.
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Well it's a D latch. Here's the code:
IF(CLRn='0')THEN
underflow_pulse_out_1<='0';
ELSIF(rising_edge(CLK))THEN
undeflow_pulse_out_1<=underflow_pulse_in;
END IF;
IF(CLRn='0')THEN
underflow_pulse_out_2<='0';
ELSIF(rising_edge(CLK))THEN
undeflow_pulse_out_2<=underflow_pulse_out_1;
END IF;
CounterUnderflow<='1' When (CounterValue=0)ELSE '0';
underflow_pulse_in<=CounterUnderflow AND CounterEnable;
I don't think there's anything wrong with it. Then again I don't have a lot of XP with VHDL.
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