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There are no limits on counters in hardware, or with certain types in VHDL. They will underflow or overflow quite naturally, and it becomes useful to do so in some circumstances.
So
FF + 1 = 0
0 - 1 = FF
I am very worried that you can have 4 "clocks" - that is very very bad design form. You need to use these 4 inputs as enables, and run the whole system off a single base clock.
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No, no, I think you might have misunderstood.
These 4 signals are not actually fed into the counter clock input, but to the counter enable so that the counter decrements only when one of these pulses goes HIGH. The counter's clock gets its signal from the main clock signal. Sorry if I wasn't clear on this.
Sorry to repeat the question, does this mean that the FF value is normal?
On a different note, I have 2 latches that are supposed to delay the signal by 2 clock edges, but I got only 1:confused: I am starting to wonder whether SignalTap is playing with me or maybe Cyclone II is going kaputt?
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