Honored Contributor
Honored ContributorSo it's normal behaviour then for the counter to go FF after 00? Could you please elaborate more?
Well about the base_clk signal, it is indeed actually a sort of a "clock" signal, as the user can use 4 different clock frequencies to run his counter with. The signal is derived from a PLL signal whose input is from the main clock signal. The counter has to have different options for starting countdown and reload, that's why its conditions take a train load of input signals. It's not really my choice to do it rather it's a project requirement. Does adding a latch or two sync these inputs help in any way?
