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metaprogrammer
New Contributor
New ContributorCould not find a way to report a Quartus bug
It appears that Verilog preprocessor in Quartus is not quite standard-conformant, the usual string concatenation trick does not work. For example, the following will fail: `define PREFIX .
`define...
metaprogrammerNew Contributor
New ContributorHi KYeoh, thanks for your answer!
I was under impression (from the detailed error messages), that the `" directive worked as expected, and it was the expansion order that was incorrect. Maybe I'm wrong, I'll try to construct more tests to check this.
As for the expansion order, it's specified in IEEE 1364-2001, par. 19.3.1.
