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Altera_Forum
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18 years ago

Correct way to use Components?

I want to use a component in my VHDL code but I'm not sure if I'm doing it correctly. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all;...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Please do give it a try, it makes an enormous difference! Even more so if (like the OP) your components are being placed in the architecture, rather than a package, so when an entity changes, you have to update it in lots of places...

Cheers,

Martin