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Altera_Forum's avatar
Altera_Forum
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18 years ago

Correct way to use Components?

I want to use a component in my VHDL code but I'm not sure if I'm doing it correctly. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all;...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

a FPGA has no internal tristate-drivers, but you can use virtual tristate drivers and bidrectional busses for internal connections anyway. The HDL synthesizer converts them to multiplexers. The problem is, that a signal can't have more than one driver. This isn't actually different from real bidirectional busses, but the HDL synthesizer must be able to see at any time which signal drives the "bus" to infer a multplexer. A set of mutual exclusive "chip select" conditions can do.

Regards,

Frank