Corner PLL negative Input

I want to use the PLL_L1_CLKn Input Pin (C39) of an EP3SL200F1517 Device to drive a PLL. If I use the positive PLL_L1_CLKp Pin (C38) Quartus fit correctly.

If I use the PLL_L1_CLKn Pin Quartus abort returning the following error: "Can't place Left/Right or Top/Bottom PLL "Simple_PLL:Simple_PLL_inst|altpll:altpll_component|Simple_PLL_altpll:auto_generated|pll1" in target device due to device constraints"

The Stratix III Device Handbook at table 6-7 (page 159) state that PLL_L1_CLKn can be used as a single ended PLL Input for PLL L1 but has to use the global network to drive the PLL:

Note 2 apply to the PLL_L1_CLKp and PLL_L1_CLKn Pin:

(2) If both PLL_<L1/L4/R1/R4>_CLKp and PLL_<L1/L4/R1/R4>_CLKn pins are not used as a pair of differential clock pins, they can be used independently as single-ended clock input pins.

Note 3 apply only to the PLL_L1_CLKn pin:

(3) For single ended clock input, CLKn pins use the global network to drive the PLLs.

I tried to apply "global clock" clock assignments and to add a CLKCTRL core but the fitting error remain.

How can I configure the design to feed the PLL L1 from PLL_L1_CLKn thru the global network?