Cordic sincos function: how to depict a fixed point number as std_logic_vector type

Question

Hello,

i want to use the Cordic sincos IPcore (https://www.altera.com/en_us/pdfs/literature/ug/ug_cordic.pdf). The input is a std_logic_vector in the range of [-pi, pi] for signed configuration case.

The input consists of: 1bit for sign, 2 bits representing the range, and the rest is the number of fractional bits.

Now, my aim is to make sine calculations for theta from 0 to 360°.

I want to start by -pi and increment by 1° = 0.017453292 for 360 times to reach one period.

So to cut a long story short:

- how can i convert the fixed point value into std_logic_vector type?

- where do i know, where my fractional bits are beginning in the std_logic_vector representation?

Thanks in advance and best regards!

altera_forum · Answer

1. No conversion is necessary. You've already said that the IP core uses fixed point representation, so your slv constains fixed point numbers.

2. With fixed point, each bit represents an decreasing 2^n, with the value in 2s compliment format

So, the MSB will be the sign bit (if signed).

The integer bits (range bits) just represent standandard integers. 01 = 1, 10 = 2, 11 = 3 etc.

The fraction bits represent values of 2^n where each value of N is negative,

eg, if you have 4 fracrtion bits, then then 1000 = 0.5, 0100 = 0.25, 0010 = 0.125, 0001 = 0.0625 etc

So the bits here represent 2^-1 downto 2^-4 etc.

The more bits you have, the better the accuracy you get.

This is simply just integers with a gain of 2^-N, where N is the number of fraction bits.

altera_forum · Answer

Wouldn't it make more sense to use a simpler unit for angular phase?

There's also a cool discussion explaining how a cordic works, here (http://zipcpu.com/dsp/2017/08/30/cordic.html). Sample code is posted on github (https://github.com/zipcpu/cordic/blob/master/rtl/cordic.v), so you can see what it does an how it works.

Dan

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