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Altera_Forum
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10 years ago

Converting Aynchronous UART to Synchronous USART

OpenCores has a very stable uart (attached) that integrates easily to altera/qsys. My goal is to tweak it just enough so that it transmits on the rising edge and receives on the falling edge of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Yes, you can latch the Rx data on a 'sync clock'. However, isn't that over complicating it? I'm assuming you'll then have to transfer the recovered data onto the 'system wishbone clock' domain. Why not just use that clock - as the original design (almost certainly) does? And how are you intending to generate the 'sync clock'?

Cheers,

Alex