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pnp's avatar
pnp
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5 years ago
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Converting a BDF diagram to HDL for simulation in Quartus Prime Pro >= v20.4

I have a legacy .bdf in my design that I need to simulate. In Quartus II, I could do this with File | Create/Update | Create HDL Design File for current file. In Quartus Prime Pro 20.4, this option ...
  • RichardT_altera's avatar
    RichardT_altera
    5 years ago

    Hi @pnp

    Unfortunately, Quartus Pro does not support this feature a few years ago.

    The current workaround is to convert it in Quartus Standard Edition and add the HDL files back to Quartus Pro.

    It is a bit tedious and I am sorry if it cause any inconvenience.

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
5 years ago

Richard,

Thanks for confirming that. I will keep this in mind--it gives me even more motivation to rewrite these old modules in SystemVerilog

I was able to get to the cause of my issue through the use of SignalTap instead of the simulator, which I posted here. It looks like that bus reversal may be a bug in the software.

Regards,

Paul

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi @pnp

Thank for confirming the answer that I have provided previously. I believe another agent will look into your other case and they will help to address your question soon.

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

  • pnp's avatar
    pnp
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thanks, Richard. I appreciate your help with that.

    Paul