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Altera_Forum
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18 years ago

Controlling Verilog `define macro with Quartus setting or script

Some Verilog designs use a `define statement, possibly located inside a file referenced by an `include statement, to control something managed with `ifdef or `ifndef. Instead of using a `define stat...
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Altera_Forum
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18 years ago

There is another solution when running Analysis & Synthesis from the command line or in a compile script using the quartus_map command. The Quartus handbook shows how to specify Verilog macros on the quartus_map command line. See Volume 1, Section III, Chapter 8 "Quartus II Integrated Synthesis" at Language Support --> Verilog HDL Support --> Verilog HDL Macros.