contraints for polled/static interfaces

Thanks for your replies, they provide me with some light about the approach to take.

Until now, I was using multicycle directives to relax timings on those pins. However, even with the docs & slides found on Altera's site, I never managed to find out which values and which of -start/-end to use for non-clock related pins.

My current constraint file contains entries like : eg.

proc set_multicycle_unh {ns nh from to} {

set_multicycle_path -from $from -to $to -setup -end $ns

set_multicycle_path -from $from -to $to -hold -end $nh

}

proc set_multicycle_xnh {ns nh from to} {

set_multicycle_unh $ns $nh $from $to

set_multicycle_unh $ns $nh $to $from

}

set_multicycle_xnh 4 4 $BUS12_GPIOS *

set_multicycle_xnh 4 4 $UARTS_GPIOS *

Is this correct ? If not, how do you advise to modify the parameters and what does it mean in term of timing calculations for the non-clock related pins ?

I'll have a try with set_min_delay=0 and set_max_delay=huge_value for non-clock related pins as well as false paths for switches.