Contraint for multi-cycle clock latency

Hello Ese002,

I do have the same problem. All the answer of the others are not really helpfull.

I try to describe my system:

I have one Clock Source (148.5 MHz).

This clock drives my FPGA pin and the Clock Pin of a second device.

The FPGA drives a Data to the second device.

I use a FPGA PLL (Cyclone IV E). After the PLL I have a Clock Switch (Megawizard)

My Clock Delay from Input to Output is more than one Clock period.

I have to define my Setup Hold Time via an Virtual Clock. This is the Problem.

Timequest now sees the complete Delay between both Clocks.

I did not find a solution except, defining an Clock to an Output Pin which is Source Synchron to the external Clock and do my Setup Hold time to this Clock.

Did not get it untill now.

Any Suggestion ?

Matthias