Contraint for multi-cycle clock latency

One more question: what FPGA family are you using?

Anyway... 2-4 ns is normal but 5-7.5 ns is big and it's because you aren't using one of the dedicated clock input pins.

But well, you're stuck with it. Some things I'd try.

a) Pass the clock though a LCELL primitive.

Non-dedicated clock pins can't drive the global/regional clock networks directly and Quartus will often route these signals as if they were normal signals.

Adding a LCELL primitive between the pin and the clock signal used to drive the logic will make Quartus route the LCELL's output using the global/regional clock network.

b) when setting the set_output_delay constrains, shift the max/min delay value by 1 clock cycle

c) use a PLL.

Use the PLLs output clock to drive your logic. "Normal compensation mode" or manually setting the PLL's output phase might help.