Contraint for multi-cycle clock latency

It is not a dedicated clock pin but it is clock capable. Moving to dedicated pin is, unfortunately, not an option. The input pin drives a regional clock buffer. Judging from other paths in the timing report, the latency on this clock is not unusual. The catch is that for internal paths and even outputs clocked from internal sources, clock latency doesn't really matter. As long as both source and destination flops see the clock at nearly the same time, the actual flight time from the clock's origin is not important. It matters for this case because the off chip components see the original clock, not the delayed form distributed inside the FPGA.

The latency values I see are large but they are not *that* unexpected. Years ago I had a Xilinx design that was sensetive to clock latency. On a large Virtex 4 device, a typical latency for a global clock was between 3 and 4ns. Regional clocks were closer to 2ns.