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Altera_Forum
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14 years ago

Contraint for multi-cycle clock latency

I have a very fast clock driven from the outside that, due to board level protocol out of my control, this clock must be used to drive data back to the source. The problem is that the latency throug...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The clock period is about 3.6ns. It takes somewhere between 5ns and 7.5ns for the clock to propagate through the input pad and the internal network to the output flops. The trouble with the large negative output delay is that the phase difference between internal and external clocks still matters, even if the total delay doesn't.