Contraint for multi-cycle clock latency

Ah, I misunderstood your problem then.

The multi-cycle part confused me.

So, let's see if I got it right this time:

You have a fast clock and your FPGA has to output signals at that fast clock's frequency. Those signals will then be received by another device in your board, running at the same clock frequency. Because there isn't any kind of feedback from your receiver to the FPGA, the delay from the FPGA to the receiver can be larger than one clock.

Is this correct?

If so, this is a pretty normal situation. And using realistic output delay (set_output_delay -min and -max) constrains looks like the correct path.

What's the operating frequency and what would the realistic output delays be?

Check if the fitter is packing the output flip-flops into the IOBs, though.