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Altera_Forum's avatar
Altera_Forum
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14 years ago

Contraint for multi-cycle clock latency

I have a very fast clock driven from the outside that, due to board level protocol out of my control, this clock must be used to drive data back to the source. The problem is that the latency throug...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I don't see how any pipe stages would do anything but it make the problem worse. Internal timing is fine. The setup violation is between the output flop and the board. Even if there was no delay at all for the data, it would still fail.