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Altera_Forum's avatar
Altera_Forum
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14 years ago

Contraint for multi-cycle clock latency

I have a very fast clock driven from the outside that, due to board level protocol out of my control, this clock must be used to drive data back to the source. The problem is that the latency throug...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If I understood your problem correctly, this is not a job for timing constrains.

Instead, you need to pipeline your design. That is, add layer of registers.

It should be easier to start adding them at the input and output levels.

Then enable the register re-timing options in the synthesis and fitting.