continuous averaging using VHDL

@kaz,

I have 2 questions related to the continuous averaging.

First question is related to increasing the number of stages. I want to increase the number of stages from 32 to 1000. I am doing this for stabilizing the ADC current values. Do I have to modify the signal lengths in the following way:

data_in  : in  std_logic_vector (31 downto 0);
type type1 is array (1 to 999) of std_logic_vector(11 downto 0);
signal stage: type1 := (others => (others => '0'));
signal sub_result: signed(12 downto 0) := (others => '0');
signal sum: signed(16 downto 0) := (others => '0');
signal stage2: type1 := (others => (others => '0'));
signal sub_result2: signed(12 downto 0) := (others => '0');
signal sum2: signed(16 downto 0) := (others => '0');

The second question is: I was not getting correct values before but now with the following approach I get the correct values. Can you see and tell if the following way looks fine. It is working correctly but Is there a better way to do this? I used the same approach as u told me but in a different way. I need to average in parallel. The code is following:

data_in  : in  std_logic_vector (31 downto 0);
type type1 is array (1 to 31) of std_logic_vector(11 downto 0);
signal stage: type1 := (others => (others => '0'));
signal sub_result: signed(12 downto 0) := (others => '0');
signal sum: signed(16 downto 0) := (others => '0');
signal stage2: type1 := (others => (others => '0'));
signal sub_result2: signed(12 downto 0) := (others => '0');
signal sum2: signed(16 downto 0) := (others => '0');
process (clk, reset)
begin
    if (reset = '1') then 
    state<=idle;
    out_val=0;
    out_val_2 <= 0;
    avg_1 <= 0;
    avg_2 <=0;
    elsif(rising_edge(clk)) then
    case state is
when idle =>
    if req='1' then 
    state= out_1;
    end if;
when out_1 =>
    if done='1' then
    data_out <= addr0 & bits;
    
    stage(1) <= data_in(11 downto 0);
for i in 2 to 31 loop
    stage(i) <= stage(i-1);
end loop;
-- subtract last stage from input
 sub_result <= resize(signed(data_in),13) - signed(stage(31));
-- accumulate
sum <= sum + sub_result;
adc_a_out <= std_logic_vector(sum(16 downto 5));
    avg_1 <= '1'; 
    state <= out_2;
    endif;
when out_2 =>
   if done='1' then
   data_out <= addr1 & bits;
   stage2(1) <= data_in(11 downto 0);
for i in 2 to 31 loop
    stage2(i) <= stage2(i-1);
end loop;
-- subtract last stage from input
sub_result2 <= resize(signed(data_in),13) - signed(stage(31));
-- accumulate
sum2 <= sum2 + sub_result2;
adc_b_out <= std_logic_vector(sum2(16 downto 5));
   avg_2 <= '1';
   state <= done_st;
when done_st =>
    ack <='1';
    state <= idle;
when others =>
    state <= idle;
    end case;
    end if;
    end process;

Many Thanks.