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Altera_Forum
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9 years ago

Constraints for Multiplexed Clocks

I have an Arria V design that has 4 clocks: base_clk : from device pin to PLL input clk_1x : 1x output from PLL (same frequency as base_clk) clk_2x : 2x output from PLL (twice freque...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Yes, the "get_nets" should have been "get_ports" for my example (unfortunate typo).

Your suggestions make sense and I will try to implement these in my next build and TimeQuest runs.

Thanks for your help!