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Altera_Forum
Honored Contributor
8 years agoConstraint Qsys IP Addressable Memory Range
Hi everyone, A few weeks ago I migrated from Xilinx to Altera/Intel ecosystem and I am facing some problems that I don't know how to fix because of the lack of experience with Quartus tool. ...
Altera_Forum
Honored Contributor
8 years agoThanks for the answer!
The "Address Span Extender" is exactly what I was looking for. At the beginning, I thought also about changing the DDR controller to address only 2GB data but in the near future some SGDMAs will be streaming data from the totality of the 4G DDR and the interface must be able to handle that. I am going to have a look at the control port of the "Address Span Extender", knowing that I can change the base address of the subwindow in software and access the whole 4GB data is a nice add-on to my test routine. Thanks again for the information!