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Honored Contributor
Honored ContributorConstraining timing on configurable PLL output for a range of frequencies
Hi I am using re-configuration feature in Altera FPGAs PLLs, so I am generating a highest frequency of 300 MHz and a lowest frequency of 25 MHz and bunch of frequencies in between on the fly. ...
Altera_ForumHonored Contributor
Honored ContributorWhat is this information you've come across that suggests you need to constrain for a lower limit? Excessive combinatorial delays only compromise a maximum working frequency - unless you have combinatorial feedback which, unless very carefully considered, I'd consider very bad practice.
If you're seeing bad behaviour when operating at your lower frequency only then I think you need to be a little more specific with what you're seeing. Cheers, Alex
