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Altera_Forum
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8 years ago

Constraining timing on configurable PLL output for a range of frequencies

Hi I am using re-configuration feature in Altera FPGAs PLLs, so I am generating a highest frequency of 300 MHz and a lowest frequency of 25 MHz and bunch of frequencies in between on the fly. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

What is this information you've come across that suggests you need to constrain for a lower limit? Excessive combinatorial delays only compromise a maximum working frequency - unless you have combinatorial feedback which, unless very carefully considered, I'd consider very bad practice.

If you're seeing bad behaviour when operating at your lower frequency only then I think you need to be a little more specific with what you're seeing.

Cheers,

Alex