Constraining SOPC Builder designs using TimeQuest

Very useful stuff for me. One question if anyone is still paying attention to this years old thread.

On page 9 of the document where it is explaining constraining SDRAM it gives the following snippet:

--- Quote Start ---

The set_input_delay and set_output_delay commands can be used to set the I/O constraints. In the examples below, a common PCB routing delay of 0.5 ns ± 0.1 ns is used resulting in 0.4 ns or 0.6 ns being added to the timing information from the SRAM data sheet.

set_input_delay -clock sdram_clk_pin -max [expr 5.5 + 0.6] <ports>

set_input_delay -clock sdram_clk_pin -min [expr 2.5 + 0.4] <ports>

set_output_delay -clock sdram_clk_pin -max [expr 2.0 + 0.6] <ports>

set_output_delay -clock sdram_clk_pin -min [expr -1.0 + 0.4)] <ports>

In each of these commands, <ports> should be a list of I/O ports for the relevant constraints as shown in the example below:

set_output_delay -clock sdram_clk_pin -max [expr 2.0 + 1.2]

[get_ports {cas_n ras_n cs_n we_n addr[*]}]

--- Quote End ---

I noticed that all of the memory access signals are included in the get_ports except for the data lines. Was that intentional or an error? Don't you need to specify the delay for the data lines as well in relation to the clock as well for when you are writing to the SDRAM?

Thanks,

David