Constraining SOPC Builder designs using TimeQuest

Hi, i'm trying to constrain my sdram controllers according to this post, but still have a few things that aren't clear.

1.) When assigning SDRAM pins to fast input and fast output registers. What do you do for the data lines that are bidirectional? Do you only set these to fast input or fast output or both?

2.) My design has a 50Mhz off chip oscillator feeding an internal pll and out of the pll is an 80Mhz clock that goes straight out a pin to an SDRAM and also internally the 80M clk drives my sdram controllers. I'm using a cyclone III. Should I break it up and use 2 clocks, 1 for the sdram clock pin, and one to drive my sdram controllers? Or will following this thread get me working with the single 80Mhz clock running everything?