Constraining SOPC Builder designs using TimeQuest

Very good documentation. Many thanks.

However, I have some questions.

(1) From Altera TimeQuest seminar, max output delay = (PCB) max data delay + (external device) tSU - min (PCB) clock delay. It is different from the "max output delay" in the document. The same is for min output delay and max/min input delay.

(2) From the document, slow asychronous I/Os such as PIO, uart, and SPI can be ignored by setting them to false paths within Quartus-II but outside of SOPC builder. Should the timing within the SOPC builder such as avalon fabric/bus be considered? Does the SOPC look after them automatically once they are set to false paths externally? The same question is for any new components in HDL.

(3) The clocks for a dual port on-chip ram can be considered independently. However, the clocks are used somewhere else in the design. In those places, they are pure multiple clocks. How can you handle that?