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Altera_Forum
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18 years ago

Constraining SOPC Builder designs using TimeQuest

This document discusses how to constrain designs based upon SOPC Builder using the TimeQuest timing analzer. The constraints discussed in this document are associated with specifying clocks, I/O tim...
Altera_Forum's avatar
Altera_Forum
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17 years ago

I'm looking through the updated document Graham posted. I'll freely admit this is my first time using TimeQuest, and it's been more than 8 years since I had to do timing analysis (was working on other technology for a long time). The document is helping clear up a lot of misconceptions I had after viewing the Altera online training.

Can someone help me walk through the section on constraining RAM interfaces? I'm working on a platform based on the Arrow LPRP, which uses Micron Cellular RAM MT45W4MW16BCGB (and the Arrow SOPC builder components for the device).

Primarily, I'm lost by the explanation of how worst case timing is pulled from the datasheet - should I be looking for the lowest value in "access time" & "hold time" and the highest values in "setup time"?

Thanks,

--Mickey