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This is an amazing resource! Timing constraints is probably the least understood aspect of FPGA development... and the most likely to get you banging your head against a wall asking god why nothing's working. And this document is the best, most clear explanation that I've found. (Which is to say: Altera, why don't you have any good docs on TimeQuest ?!?!) I also love the sheer style and organization.
However, I'm pretty sure page 9 is all wrong. I.e., using datasheet timing data to constrain an external interface. First of all, it is the max output delay (ie input setup time) that is negative, not the min output delay (the hold time). Reason for this is simple. The max output delay should be a large number, just like the max input delay. However, "setup time" is usually quoted as time _to_ the clock edge (eg 2ns) not from it (eg 18ns). So you have to negate it. Hold time, meanwhile, is quote _from_ the clock edge just like other delays.
The SDC should look like this:
create_generated_clock -name sdram_clk_pin -source $sdram_clk -offset 0.5 [get_ports {sdram_clk}]
set_input_delay -clock sdram_clk_pin -max [expr 5.5 + 0.6] <ports>
set_input_delay -clock sdram_clk_pin -min [expr 2.5 + 0.4] <ports>
set_output_delay -clock sdram_clk_pin -max [expr -2.0 - 0.6] <ports>
set_output_delay -clock sdram_clk_pin -min [expr 1.0 - 0.4] <ports>
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I have done some experimentation and believe that it IS the minimum output delay that should be negated. This is something I was told when I first start using TimeQuest. I am not sure why but I have given up trying to understand this long ago and now I just accept it.
For my experiment I implemented a D type FF in Quartus and ran TimeQuest with the following commands:
create_clock -period 20 [get_ports {clk}]
set_output_delay -clock clk -min -1.0 [get_ports {q}]
You can see from the diagram attached that the effect of the output delay is to push the data required time out to the right which equates to a hold time of a device whose input is conected to the output of my FPGA.
There is a typo in the doc though as the example:
set_output_delay -clock sdram_clk_pin -min [expr 1 – (1.0 + 0.4)] <ports>
should read
set_output_delay -clock sdram_clk_pin -min [expr 0 – (1.0 + 0.4)] <ports>
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