Constraining SOPC Builder designs using TimeQuest

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The two related clocks (clk_a and clk_b) are created at page 4 of the document attached to the 1st post.

These clocks have periods of 10 and 20 ns respectively as shown at the picture.

Is it correct?

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The waveforms show 10 ns and 20 ns period but the example SDC commands do not reflect this. The correct SDC commands are:

create_clock –period 10 –waveform {0 5} [get_ports {clk_a}]

create_clock –period 20 –waveform {3 13} [get_ports {clk_b}]