Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Constraining SOPC Builder designs using TimeQuest

This document discusses how to constrain designs based upon SOPC Builder using the TimeQuest timing analzer. The constraints discussed in this document are associated with specifying clocks, I/O tim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Oh, one more thing. Template# 2 assumes that the target is pipelined. Ie, you give it a command on one clock cycle, you get the response on the next. If the target works more like a combinational circuit, use this: 

set_input_delay -clock sdram_clk_at_the_fpga_pin - max  <ports>
set_input_delay -clock sdram_clk_at_the_fpga_pin -min  <ports>