Constraining SOPC Builder designs using TimeQuest

Oh, and the .doc should explain what exactly pcb delay is. It's not just the time that electricity takes to go through a wire, like a wave spreading down a canal. It's the time to actually send enough electrons into all the capacitors that are connected to that wire. If you load up a lot of components onto the same tristate bridge or if you turn the driving current way down, you will have a big pcb delay. That's what the "pin capacitive load" means.

But modeling the load as just one big capacitor isn't too accurate (well, it's still a hell lot better than nothing!). Use Advanced I/O Timing to simulate terminations if you're at all using them. Yet for all its additions Advanced I/O still assumes that the far-end load is just a capacitor. If you read DDR2 datasheets, for example, they'll often not tell you the capacitive load at all and instead print a warning that it's not so simple and that you should go use an IBIS file (which essentially replaces a single number with a graph). Third-party SI tools aren't that hard to use. HyperLynx in particular has a very easy interface.

But if you're not tight in your timing budget, don't get anal about things. Just insert safe guesstimates. If you don't even want to specify an Advanced I/O Timing model or dig through datasheets, you don't really have to. You don't need to spend the time to do that, but you DO have to follow template# 2 and insert appropriate guesstimates.