Constraining SOPC Builder designs using TimeQuest

I've been thinking a bit more about this and realized the stuff about board delay is off too.

Quartus II already compensates for pcb delay! Both in the clock and in the signals. It uses either capacitive load or a board model to calculate pcb delay and include it along with logic and fabric delay when meeting timing. (Of course you have to fill in all the data correctly first.) However it does this half-assedly. Literally. It only does this on the output pins, not the input puts.

If relying on Quartus's internal simulation and not using third-party SI tools, then the section of the SDC file should look like this. Note that neither the clock nor the output_delay is explicitly corrected while input_delay is corrected only for the trip back.

create_generated_clock -name sdram_clk_at_the_sdram -source $sdram_clk 
set_output_delay -clock sdram_clk_at_the_sdram -max  <ports>
set_output_delay -clock sdram_clk_at_the_sdram -min  <ports>
set_input_delay -clock sdram_clk_at_the_sdram -max  <ports>
set_input_delay -clock sdram_clk_at_the_sdram -min  <ports>

If you ARE using third-party SI tools, set capacitive load for each pin to zero (and disable all the resistors and capacitors in the board model) to turn off Quartus' corrections. Then plug your precise board delay figures (or your conservative estimates) into the following. Keep in mind what the meaning of "longest" and "shortest" is. It could be you're putting several different signals in one command. But even a single signal will take a different time on a low-to-high transition than a high-to-low (not counting general randomness). Also remember that a signal hasn't transitioned until the voltage reaches the appropriate threshold. If you're jerry-rigging 3.3v TTL to 5v TTL, for example, then you have to keep this in mind when using your SI tools.

create_generated_clock -name sdram_clk_at_the_fpga_pin -source $sdram_clk 
set_output_delay -clock sdram_clk_at_the_fpga_pin -max  <ports>#  sometimes the signal lags behind the clock. the max is lowered.
set_output_delay -clock sdram_clk_at_the_fpga_pin -min  <ports>#  sometimes it speeds ahead. the min is raised.
set_input_delay -clock sdram_clk_at_the_fpga_pin - max  <ports>
set_input_delay -clock sdram_clk_at_the_fpga_pin -min  <ports>

Note that you still have to create_generated_clock. Even with the pcb delay compensations turned off, it still calculates the fabric delay of the clock getting to that pin. If you use "zero delay buffer" and a dedicated PLL out then you can probably do without it. But I'm not sure you even need a zero delay buffer if you build your SDC file like this.