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Altera_Forum
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18 years ago

Constraining SOPC Builder designs using TimeQuest

This document discusses how to constrain designs based upon SOPC Builder using the TimeQuest timing analzer. The constraints discussed in this document are associated with specifying clocks, I/O tim...
Altera_Forum's avatar
Altera_Forum
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18 years ago

The two related clocks (clk_a and clk_b) are created at page 4 of the document attached to the 1st post.

These clocks have periods of 10 and 20 ns respectively as shown at the picture.

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These can be assigned with the following commands:

create_clock –period 10 –waveform {0 5} [get_ports {clk_a}]

create_clock –period 10 –waveform {3 13} [get_ports {clk_b}]

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Is it correct?