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Altera_Forum
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18 years ago

Constraining SOPC Builder designs using TimeQuest

This document discusses how to constrain designs based upon SOPC Builder using the TimeQuest timing analzer. The constraints discussed in this document are associated with specifying clocks, I/O tim...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Thanks for the hint!

I couldn't get back earlier, but now I should have tuned the PLL phaseshift correctly and I get no violations in the slow model. The fast model on the other hand has hold violations of about -2ns on all data (inout) lines and I seem to have no margin to get rid of this -2ns slack. All timing optimizations are already turned on.

Well I better get started with the documentation...