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Altera_Forum
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18 years ago

Constraining SOPC Builder designs using TimeQuest

This document discusses how to constrain designs based upon SOPC Builder using the TimeQuest timing analzer. The constraints discussed in this document are associated with specifying clocks, I/O tim...
Altera_Forum's avatar
Altera_Forum
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18 years ago

If you are seeing setup violation and no hold violations on your SSRAM and/or SDRAM timing then it would suggest that the PLL used to offset the clocks to these devices is not set up correctly.