Constraining SOPC Builder designs using TimeQuest

Thanks for the tutorial!

Do you happen to still have the complete demo-design with the tested SDC file(s)? I am one of those who never had timing issues with their small/medium designs before, but now have...

I am especially interested in properly constraining SDRAM/SRAM with Timequest - I followed your tutorial closely but for some reason my design fails all setup requirements for my SDRAM/SRAM input paths by a slack of about -5ns. This is @60MHz on a CycloneII quite much.

Additionally there are setup violations for the ssram_clk_pin and sdram_clk_pin nodes - is this supposed to be not analyzed by a falsepath setting?

Snippets from my SDC file (my SDRAM has the same characteristics as used in the tutorial):

# **************************************************************
#  Create Clock
# **************************************************************
#  both clock inputs are from the same crystal
#  feeds PLL for system clock and SDRAM
create_clock -name {INCLK0} -period 30.518  
#  feeds PLL for SSRAM
create_clock -name {INCLK1} -period 30.518  
# **************************************************************
#  Create Generated Clock
# **************************************************************
derive_pll_clocks
create_generated_clock -name {sdram_clk_pin} -source {clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk} -offset 0.500 
create_generated_clock -name {ssram_clk_pin} -source {clkgen1|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk} -offset 0.500 
derive_pll_c
# **************************************************************
#  Set Input Delay
# **************************************************************
set_input_delay -max -clock sdram_clk_pin  6.100 }]
set_input_delay -min -clock sdram_clk_pin  2.900 }]
.
.
# **************************************************************
#  Set Output Delay
# **************************************************************
set_output_delay -max -clock sdram_clk_pin  2.600 }]
set_output_delay -min -clock sdram_clk_pin  -0.400 }]
.
.

TOP failing paths:

slack	From Node	    To Node					  Launch Clock	    Latch Clock
-5.750	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.750	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.739	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.739	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.732	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.732	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.730	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.730	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.730	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.725	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.725	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.722	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.722	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.720	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.714	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.714	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.712	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.709	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.706	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.706	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.705	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.705	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.702	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.702	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.702	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.702	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.702	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.701	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.701	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.701	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.690	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk
-5.680	DRAM_DB	sdctrl:\sdc:sdc|r.hrdata	sdram_clk_pin	clkgen0|\alt:v|sdclk_pll|\nosd:altpll0|pll|clk

Thanks for any hints or answers - and yes, I probably shouldn't follow blindly tutorials, but actually read the QII handbook to get my constraints right...